The ever increasing demand for higher density devices for use in for instance integrated circuits (ICs) and micro electromechanical structures (MEMS) has led researchers and manufactures to investigate the use of high aspect ratio structures in such devices. High aspect ratio structures offer large surface areas but have a relatively small footprint, making them suitable for use in for example high density capacitors, batteries, biosensors and the like.
One method for increasing the surface area of a silicon substrate comprises etching pores or trenches into the substrate. A known problem with this approach is that the degree of diffusion of an etchant rapidly decreases near the bottom of a pore or trench. This phenomenon, called Aspect Ratio Dependent Etching (ARDE) has two effects: it leads to uneven etching rates along the depth of the pore or trench and also requires longer etching times to reach the same depth for narrower features.
To address this problem it has been proposed to etch pillars instead of pores into a substrate. Pillars and pores of the same diameter have essentially the same surface area. However, the larger amount of free space around the pillars on the substrate enables a greater degree of diffusion of an etchant or, in case of subsequent layer deposition, of gas or vapor species. A disadvantage of using pillar structures is that they are more fragile and likely to break due to mechanical stress during handling and/or further processing. When an array of pillars is arranged on a substrate, thermal expansion of the substrate can damage the pillars, especially near the periphery of the pillar array fields, where local symmetries and topologies in the design are disrupted.
A pillar structure offering improved stability has been disclosed in WO 2007/125510. The disclosed invention relates to an semiconductor device including an electric element, the electric element comprising a first electrode having a first surface and a pillar, the pillar extending from the first surface in a first direction, the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section perpendicular to the first direction and the pillar having a sidewall surface enclosing the pillar and extending in the first direction, wherein the pillar comprises any one of a score and protrusion extending along at least part of the length of the pillar for giving the pillar improved mechanical stability.
In an embodiment, a plurality of such pillar electrodes is arranged in an array. Although the document mentions that the symmetry and ordering of the pillar array preferably is such that the free space around pillars is evenly distributed over the array area, the document does not mention how this can be achieved other than by placing the pillars in an equidistant grid. Furthermore, the prior art document does not offer a way to reduce the detrimental effects which differences in thermal expansion within an array can have on pillar structures.
It is an object of the present invention to provide an semiconductor device comprising improved mechanically robust high aspect ratio structures offering a high degree of diffusion.
It is a further object to provide an semiconductor device comprising mechanically robust high aspect ratio structures which are better adapted for withstanding thermal differences in the device during the manufacture and/or operation thereof.